1. Field
Embodiments of the invention relate to the field of instruction translation.
2. Background Information
Binary translation may be performed in order to translate source code of a source instruction set architecture (ISA) that is suitable for a source machine or processor to target code of a target ISA that is suitable for a target machine or processor on a target operating system. In the binary translation, source instructions of the source ISA may be translated to target instructions of the target ISA.
In some translations, the source ISA may be a hybrid ISA, while the target ISA may be a unitary ISA. A hybrid ISA may have one or more multi-format instructions that may use the same or similar semantics to operate on data having different formats, such as, for example, integer and floating point formats. An example of a hybrid ISA is the IA-32 ISA, of Intel Corporation, of Santa Clara, Calif. The IA-32 ISA includes the Intel® Streaming SIMD Extension instructions, such as, for example, the SSE, SSE2, and SSE3 instruction sets. In the IA-32 ISA, certain registers, such as the 128-bit XMM registers, are multi-format registers that may store data having different formats. For example, a register may include 128-bits that may be used to store four 32-bit packed single precision floating-point data elements, two 64-bit packed double precision floating-point data elements, or one 128-bit integer data element. The MOVAPD, MOVAPS, and MOVDQA instructions of the SSE, SSE2, and SSE3 instruction sets are multi-format instructions that use the same or similar semantics to move data having different formats between XMM registers and/or between XMM registers and an off-processor memory, depending upon the particular instruction.
During a binary translation, the multi-format instructions of the hybrid ISA, such as, for example, the MOVAPD, MOVAPS, and MOVDQA instructions, may be translated to code of the unitary ISA, such as, for example, code of the Itanium® architecture, which is suitable for a 64-bit Itanium® processor or architecture.
However, the unitary ISA, such as, for example, the Itanium® architecture, may have separate registers to store data of different formats and/or may allow processing of data of only floating point or only integer formats in parallel. In order to perform the binary translation, a format may be picked for the multi-format instructions. If the formats for the multi-format instructions are not picked wisely, there may be a large cost, such as, for example, in processor cycles, in order to utilize the source code on the target machine or processor.